`include "defines.v"

module regfile (
    input clk,
    input rst,
    
    //read port 1
	input  wire         rena1,
    input  wire [ 4: 0] raddr1,
    output wire [63: 0] rdata1,

    //read port 2
	input  wire         rena2,
    input  wire [ 4: 0] raddr2,
    output wire [63: 0] rdata2,

    //write port
    input  wire         we,
    input  wire [ 4: 0] waddr,
    input  wire [63: 0] wdata,

	//sim
	output reg [63: 0] rf [31: 0]
);


//write
always @(posedge clk) begin
    if (rst) begin
        rf[ 0] <= `ZERO_WORD;
		rf[ 1] <= `ZERO_WORD;
		rf[ 2] <= `ZERO_WORD;
		rf[ 3] <= `ZERO_WORD;
		rf[ 4] <= `ZERO_WORD;
		rf[ 5] <= `ZERO_WORD;
		rf[ 6] <= `ZERO_WORD;
		rf[ 7] <= `ZERO_WORD;
		rf[ 8] <= `ZERO_WORD;
		rf[ 9] <= `ZERO_WORD;
		rf[10] <= `ZERO_WORD;
		rf[11] <= `ZERO_WORD;
		rf[12] <= `ZERO_WORD;
		rf[13] <= `ZERO_WORD;
		rf[14] <= `ZERO_WORD;
		rf[15] <= `ZERO_WORD;
		rf[16] <= `ZERO_WORD;
		rf[17] <= `ZERO_WORD;
		rf[18] <= `ZERO_WORD;
		rf[19] <= `ZERO_WORD;
		rf[20] <= `ZERO_WORD;
		rf[21] <= `ZERO_WORD;
		rf[22] <= `ZERO_WORD;
		rf[23] <= `ZERO_WORD;
		rf[24] <= `ZERO_WORD;
		rf[25] <= `ZERO_WORD;
		rf[26] <= `ZERO_WORD;
		rf[27] <= `ZERO_WORD;
		rf[28] <= `ZERO_WORD;
		rf[29] <= `ZERO_WORD;
		rf[30] <= `ZERO_WORD;
		rf[31] <= `ZERO_WORD;
    end
    else if (we & (|waddr)) rf[waddr] <= wdata;
end

//read port 1
assign rdata1 = (rst | ~rena1)     ? `ZERO_WORD :
                (raddr1==5'b00000) ? `ZERO_WORD : rf[raddr1];

//read port 2
assign rdata2 = (rst | ~rena2)     ? `ZERO_WORD :
                (raddr2==5'b00000) ? `ZERO_WORD : rf[raddr2];

endmodule
